The manufacturing of electronic and optoelectronic integrated circuits (ICs) involves complex lithographic processes to form microscopic solid-state devices and circuits in semiconductor wafers. These lithographic processes typically include forming layers of material on the wafer, patterning the layers, doping the substrate and/or the patterned layers, and heat-treating (e.g., annealing) the resulting structures. These processes are repeated to build up the IC structure. The result is a wafer containing a large number of ICs.
A “wafer sort” is then performed, wherein each IC chip on the wafer is electrically tested for functionality. The wafer is then separated (“diced”) into the individual IC chips, which are then “packaged” individually or in groups for incorporation onto a “panel,” e.g., a printed circuit board (PCB) or motherboard.
The packaged dies (or “dies” for short) must be placed in specific locations on the panel to within a given accuracy so that interconnections between the dies can be successfully established. To this end, the panel includes alignment marks or “fiducials” to assist in achieving the desired placement accuracy. The dies are placed on the panel by a die placement machine, sometimes referred to as a “chip shooter.” The machine includes an optical vision system that locates and recognizes the fiducials as well as an alignment mark on the die. Information from the optical vision system relating to the position of the die relative the fiducials allows the die to be placed on the panel at a specific location.
This die placement process provides a die placement accuracy no better than about 25 microns (3 sigma). The main factor limiting the accuracy of the die placement process is the error in the placement of fiducials on the panel. To date, a placement accuracy of 25 microns (3 sigma) has been satisfactory for most die placement applications. However, for certain new packaging applications, a die placement with much greater accuracy (e.g., 2 microns, 3 sigma) is required. For example, in bump lithography, once the dies are mounted to the panel, further lithography steps are carried out. In particular, a print solder resist layer is deposited, and then plate metal (e.g., copper) traces are formed to establish the electrical connections between the dies. Without highly accurate die placement on the panel, the subsequent lithography steps cannot be successfully performed.
Accordingly, what is needed is a die placement apparatus and method that provides for greater die placement accuracy.